Silicon integrated circuits consists of active device regions constructed within a silicon substrate and isolated from each other by an insulator surrounding the active areas and disposed over the silicon substrate. The isolated devices are interconnected by means of conductive film traces fabricated above the insulator to form electric circuits. The isolated active devices are joined from the substrate to the conductive film traces by contacts.
This may be seen in FIG. 1 where a transistor schematic of an CMOS inverter is shown to have an NMOS enhancement mode transistor 59, a PMOS enhancement mode transistor 57 and four conductive traces; reference ground trace Vss 51, power source trace Vcc 55, input signal trace IN 53, and output signal trace OUT 60. Both transistors are coupled to input signal 53 at their respective gates. Power source Vcc 55 is connected to the source electrode of PMOS transistor 57 at contact point 64, and reference ground Vss 51 is connected to the source electrode of NMOS transistor 59 at contact point 61. Both NMOS transistor 59 and PMOS transistor 57 are connected to output signal OUT 60 at contact points 62 and 63, respectively. The contact points 61-64 serve to electrically couple the individual conductive traces and active region transistors to form an inverter circuit.
In FIG. 2, NMOS transistor 59 is shown to consist of n-type electrodes 67 divided by gate input signal IN 53 and constructed within a p-well 65. The source electrode of NMOS transistor 59 is connected to Vss 51 along contact 61, while its drain electrode is connected to signal OUT 60 by means of contact 62. Similarly, PMOS transistor 57 is constructed within an N-well 69 and consists of p-type electrodes 71 divided by the same gate input signal IN 53. The source electrode of PMOS transistor 57 is connected to Vcc 55 along contact 64 and connected to output signal OUT 60 along contact 63.
With reference to FIG. 3, NMOS transistor 59 and PMOS transistor 57 are defined in terms of film layers to form active areas within a P-substrate 70. NMOS transistor 59 consists of n-type source electrode 67a and n-type drain electrode 67b divided by input gate 53 and constructed within p-well 65. PMOS transistor 57 is constructed within n-well 69 and consists of a p-type source electrode 71b and p-type drain electrode 71a divided by input gate electrode 53. PMOS transistor 57 and NMOS transistor 59 are isolated from each other by field oxide 75, and both have a thin layer of silicide 77 on their drain, gate and source electrode for the purpose of reducing contact resistance. A layer of silicon dioxide insulator 73 covers and further isolates both transistors 59 and 57.
Using a masking step, vias, or contact holes, 72 are made in the silicon dioxide 73 penetrating from its surface to each electrode 67 and 71 of transistors 59 and 57, respectfully, as shown in FIG. 4. Although vias having an inclined slope provide for good step coverage, vertical vias 72 are shown since reduced contact size has become an important factor in advanced lithographic patterning technologies. A conductor, such as CVD tungsten 79, is then blanketed over the silicon dioxide 73. Tungsten 79 is used since it serves as both a good contact barrier between metals such as aluminum used to construct conductive film traces and the silicon electrodes 67 and 71, and also serves as a good interconnect fill for improving step coverage of the metal.
The tungsten 79 is then etched back to form a level surface with the silicon dioxide 73, as shown in FIG. 5. The tungsten 79, surrounded by silicon dioxide 73, forms contacts 61-64, as represented in FIGS. 1 and 2. Finally, a metal such as aluminum is used to form three conductive film traces 51, 60, and 55 laid over the contacts 61-64 to form lines Vss, OUT, and Vcc, respectfully, as depicted in FIGS. 1 and 2.
With reference to FIG. 7, a close-up view of the construction of a semiconductor contact shows a layer of silicon dioxide insulator 13 disposed over a silicon substrate body 12 with a vertical contact hole 11 made within the silicon dioxide insulator 13. CVD tungsten 15 is blanketed over the silicon dioxide insulator 13 and within the contact hole cavity 15. The tungsten 17 is then etched back to leave only the via, or contact, 19, shown in FIG. 8.
It is important to have good interconnect step coverage into a contact hole such that the tungsten sufficiently covers the sidewalls of the contact window and forms a relatively level surface with the surrounding silicon dioxide insulator. Otherwise, the contact may form a poor conductive path to an active device region, or irregularities on the surface of the contact may be amplified in subsequent process film layer steps, resulting in low component yields. The contact should therefore be small enough to allow a complete contact fill after the tungsten is etched back. As a result, a layout requirement is that all contacts be of a minimum dimension in at least one direction, as shown in FIG. 9. In FIG. 9, a top view of contacts 21 and 23 shows them to have respective widths, w and W, of equal size, but respective lengths l and L of different size. The width is set to a common minimum that assures good step coverage.
FIG. 10 shows a three dimensional view of a cut-out portion of two contact holes 27 and 29 of different widths W1 and W2, respectively, formed on a silicon substrate 26 and covered by a layer of tungsten 25. After etching back the tungsten 25, shown in FIG. 11, the tungsten 25 in the contact of smaller width W1 is shown to completely cover the sidewalls of the contact hole 27, providing a good interconnect step coverage. In the contact of larger width W2, however, the etching back of the tungsten 25 is shown to form residue stringers 31 along the sidewalls of contact hole 29. Therefore, if a contact of relatively large dimensions, having at least one physical dimension of a few microns or more, is constructed using prior art methods, as shown in FIG. 12, long tungsten stringers 37 will develop along the perimeter of the contact hole sidewalls 35. Because of the differences in film stress, the tungsten stringers 37 may, in whole or part, separate and lift from the sidewalls 35 and be redeposited elsewhere on a wafer surface, causing a defective device.
As a result, only minimum sized contacts are usually used in silicon integrated circuits, with larger contacts constructed as multiple contact windows placed side by side. This provides for the smallest device size possible since the minimum sized contact is commonly determined by the minimum resolution capability of a patterning technology used in the integrated circuit in which the contact is constructed, which is usually in the sub-micron range.
Laying out a circuit using only minimum dimension contacts is normally not a problem. However, the layout of certain test structures, process monitor features, and photo processing aids cannot be done using only minimum dimension contacts. For example, it may happen that a contact etch process monitor has a spot size component greater than the minimum contact size. Further, some photo alignment tools require large dimension features to be printed on wafer to accomplish alignment. Still other aligning tools require resist to be cleared over a previously printed alignment key. This is done by removing the resist in a large area over that alignment key. Additionally, if the process flow contains a "plug" implant into the contact, it is common to provide for a spreading resistance structure to monitor the implant profile. Spreading resistance structures requires a feature larger than a hundred microns to measure.
If these large contact geometries are contained on a photo mask, or wafer, the resultant previously described stringer may lift off of contact window sidewalls causing defect problems.
It is an object of this invention to provide a contact structure of large dimensions which reduces the separating and lifting off of stringers from contact window sidewalls.